From lab demonstration to merchant part

Integrated cryogenic readout is no longer speculative — national-laboratory research ASICs have demonstrated multi-channel amplification, discrimination, and picosecond time-tagging at 4 K. What does not exist is a commercial part: documented, supported, purchasable. A lab program doesn’t productize, warrant, or support silicon — and detector makers aren’t IC houses. That gap is our product.

The part we’re designing

Our first product in design is a 4 K readout ASIC for SNSPD arrays: a low-noise front-end, discriminator, and time-tagger per channel, with per-channel bias and threshold trim, serialized onto a handful of digital lines — so coax count stops scaling with channel count, inside a 4 K heat budget measured in milliwatts. Trim settings persist on-chip at operating temperature — a running array needs no per-channel traffic from room temperature, and settings survive cold power cycles with no host reload.

What we build on

• SiGe BiCMOS at cryogenic temperatures — bipolar front-ends are proven at 4 K in the published record, and the devices improve cold: current gain rises several-fold and transit frequencies climb toward half a terahertz. For low-noise analog at 4 K, SiGe is the native technology.
• A characterization-first design method — cryogenic device models are not yet part of any production PDK. We design against published cryogenic device data, validate with cryo test structures on every tape-out, and use on-chip trim to absorb residual model error.
• Open-shuttle economics — IHP’s 130 nm SiGe:C BiCMOS open process lets us iterate silicon at a cost structure sized for scientific and quantum-industry volumes. Hundreds to low thousands of units per year is a healthy business for us — not a rounding error below someone’s minimum order.

The readout architecture is patent-pending.

Setting a readout roadmap? Get in touch.